The instruction currently held in the CIR is analyzed by the Control Unit (CU) to determine what action is required.
The instruction is split into two parts: the Opcode (the operation to be performed, such as ADD or LOAD) and the Operand (the data or the memory address of the data to be used).
If the instruction requires additional data from memory, the CU prepares the MAR and MDR to fetch that specific data before moving to the next stage.
The CPU carries out the instruction identified during the decode phase. This might involve mathematical calculations, logical comparisons, or data movement.
For arithmetic or logic operations, the Arithmetic Logic Unit (ALU) is engaged, and the results are typically stored in the Accumulator (ACC).
If the instruction is a 'jump' or 'branch' command, the Program Counter (PC) may be updated with a new address, overriding the standard incrementation.
| Component | Role in Cycle |
|---|---|
| MAR | Holds the address of the current memory location being accessed. |
| MDR | Holds the actual data or instruction fetched from that address. |
| PC | Acts as a pointer to the future instruction to be fetched. |
| CIR | Holds the current instruction while it is being decoded. |
Sequence Matters: When describing the Fetch stage, always mention the PC copying to the MAR before the incrementing of the PC. Examiners look for this specific order.
Register Transfer Notation (RTN): Practice writing the cycle using RTN (e.g., ) as it is a precise way to show data movement without long descriptions.
Interrupt Check: Remember that the CPU checks for Interrupts at the end of every Execute phase before starting the next Fetch phase. If an interrupt is detected, the current register states are saved to a stack.