What is the primary difference between the Address Bus and the Data Bus?

The Address Bus is unidirectional and carries only memory locations from the CPU to other components. In contrast, the Data Bus is bidirectional, allowing data and instructions to flow both into and out of the CPU.

How does the Memory Address Register (MAR) differ from the Memory Data Register (MDR)?

The MAR holds the specific numerical address of the memory location being accessed. The MDR holds the actual data value or instruction that is being read from or written to that specific address.

What is the distinction between the Program Counter (PC) and the Current Instruction Register (CIR)?

The PC stores the address of the *next* instruction to be fetched, while the CIR stores the *actual instruction* currently being decoded and executed by the CPU.

What common error occurs when describing the direction of the Address Bus?

Students often incorrectly label the Address Bus as bidirectional. It must be unidirectional because only the CPU (or DMA controllers) specifies which memory address is being targeted for an operation.

What happens if the Program Counter (PC) fails to increment during the fetch stage?

The CPU would enter an infinite loop, repeatedly fetching and executing the same instruction from the same memory address, preventing the program from progressing.

Why is it a mistake to say the ALU stores the results of its calculations?

The ALU performs the calculation, but it does not have long-term storage. The result is immediately passed to the Accumulator (ACC) or another register for storage.

Define the 'Stored Program Concept'.

It is the fundamental principle of the Von Neumann architecture where both the program instructions and the data they operate on are stored together in the same main memory.

What is the function of the Accumulator (ACC)?

The Accumulator is a special-purpose register that serves as the primary storage for the results of arithmetic and logic operations performed by the ALU.

What is the role of the Control Unit (CU)?

The CU directs the operation of the processor by decoding instructions and sending control signals to coordinate how data moves between the CPU, memory, and I/O devices.

How does the System Clock influence CPU performance?

The clock generates pulses at a fixed frequency; each pulse represents a 'cycle' where a single action can occur. A higher clock speed allows more instructions to be processed per second.

Revision Notes

AS-Level

Cambridge International Examinations

Computer Science

4. Processor Fundamentals

System architecture

System Architecture

Summary

System architecture defines the conceptual model and operational structure of a computer system. The most prevalent design is the Von Neumann architecture, which establishes how the processor, memory, and input/output systems interact through a shared bus system and specialized internal storage units called registers.

1. The Von Neumann Model

The Von Neumann model is the foundational design for most general-purpose computers, characterized by the 'stored program' concept where both data and instructions are stored in the same memory space.

This architecture consists of a Central Processing Unit (CPU), a main memory unit (Immediate Access Store), and Input/Output (I/O) mechanisms that allow the system to interact with the external environment.

A critical feature of this model is that the CPU can access memory directly to fetch instructions, which are then executed sequentially by the processor's internal components.

The efficiency of this model relies on the seamless coordination between the processor and memory, though it is often limited by the speed at which data can be transferred between them.

Block diagram of the Von Neumann architecture showing the relationship between Main Memory, the CPU, and the I/O System.

2. Special Purpose Registers

Registers are high-speed, small-capacity storage locations within the CPU used to hold data and instructions temporarily during the fetch-execute cycle.

The Program Counter (PC) holds the memory address of the next instruction to be processed, automatically incrementing after each fetch to point to the subsequent instruction.

The Memory Address Register (MAR) stores the address of the memory location currently being accessed for either a read or write operation.

The Memory Data Register (MDR) acts as a buffer, holding the actual data or instruction that has just been fetched from memory or is about to be written to memory.

The Current Instruction Register (CIR) holds the instruction currently being decoded and executed, separating it into its opcode and operand components.

3. CPU Internal Components

The Arithmetic Logic Unit (ALU) is responsible for performing all mathematical calculations (addition, subtraction) and logical comparisons (AND, OR, NOT) required by instructions.

The Control Unit (CU) manages the flow of data through the processor and coordinates the activities of other components by sending out control signals.

The System Clock provides a continuous pulse that synchronizes all internal operations, ensuring that the various stages of the fetch-execute cycle occur in the correct order.

The Accumulator (ACC) is a general-purpose register that stores the intermediate and final results of calculations performed by the ALU.

4. System Buses

5. Key Distinctions in Architecture

6. Exam Strategy & Tips

System Architecture

Summary

1. The Von Neumann Model

A critical feature of this model is that the CPU can access memory directly to fetch instructions, which are then executed sequentially by the processor's internal components.

The efficiency of this model relies on the seamless coordination between the processor and memory, though it is often limited by the speed at which data can be transferred between them.

Block diagram of the Von Neumann architecture showing the relationship between Main Memory, the CPU, and the I/O System.

2. Special Purpose Registers

Registers are high-speed, small-capacity storage locations within the CPU used to hold data and instructions temporarily during the fetch-execute cycle.

The Program Counter (PC) holds the memory address of the next instruction to be processed, automatically incrementing after each fetch to point to the subsequent instruction.

The Memory Address Register (MAR) stores the address of the memory location currently being accessed for either a read or write operation.

The Memory Data Register (MDR) acts as a buffer, holding the actual data or instruction that has just been fetched from memory or is about to be written to memory.

The Current Instruction Register (CIR) holds the instruction currently being decoded and executed, separating it into its opcode and operand components.

3. CPU Internal Components

The Arithmetic Logic Unit (ALU) is responsible for performing all mathematical calculations (addition, subtraction) and logical comparisons (AND, OR, NOT) required by instructions.

The Control Unit (CU) manages the flow of data through the processor and coordinates the activities of other components by sending out control signals.

The System Clock provides a continuous pulse that synchronizes all internal operations, ensuring that the various stages of the fetch-execute cycle occur in the correct order.

The Accumulator (ACC) is a general-purpose register that stores the intermediate and final results of calculations performed by the ALU.

4. System Buses

Buses are sets of parallel wires used to transmit data and signals between the CPU, memory, and I/O controllers.

The Address Bus is unidirectional, carrying the location of the data being accessed from the CPU to the memory or I/O devices.

The Data Bus is bidirectional, allowing the transfer of actual data and instructions between the CPU and other system components.

The Control Bus is bidirectional and carries command signals (such as read/write requests) and status signals (such as interrupts) to synchronize system activities.

5. Key Distinctions in Architecture

Feature	Address Bus	Data Bus
Direction	Unidirectional (CPU to Memory)	Bidirectional
Purpose	Specifies 'where' data is located	Carries the 'what' (actual data)
Width	Determines max addressable memory	Determines data transfer volume

MAR vs. MDR: The MAR always contains a memory address (a location), while the MDR contains the actual contents (data or instruction) found at that address.
PC vs. CIR: The PC looks ahead to the next instruction, while the CIR focuses on the instruction currently being handled by the Control Unit.

6. Exam Strategy & Tips

When describing the fetch-execute cycle, always specify the movement of data between registers using Register Transfer Notation (RTN), such as $MAR \leftarrow [PC]$ .

Always check the direction of the buses; a common mistake is describing the Address Bus as bidirectional, which is incorrect as the CPU is the sole source of memory addresses.

Remember that the PC increments during the fetch stage, not at the end of the cycle, to ensure the processor is ready for the next instruction immediately.

Verify that your explanations of the ALU include both 'arithmetic' (math) and 'logic' (comparisons), as omitting one can lead to incomplete marks.