What is the primary difference between throughput and latency in the context of pipelining?

Throughput refers to the total number of instructions completed per unit of time, which pipelining increases. Latency is the time required for a single instruction to pass through all stages, which pipelining does not improve and may slightly increase due to stage synchronization.

How does a structural hazard differ from a data hazard?

A structural hazard occurs when two instructions require the same physical hardware resource (like memory) at the same time. A data hazard occurs when an instruction depends on the data result of a previous instruction that has not yet completed its execution or write-back stage.

What is the difference between stalling and forwarding as solutions to data hazards?

Stalling (inserting a bubble) stops the pipeline for one or more cycles until the required data is written to a register. Forwarding (bypassing) retrieves the data directly from an internal pipeline register or functional unit output as soon as it is available, allowing the next instruction to proceed without waiting.

What common mistake is made when calculating the speedup of a 5-stage pipeline?

A common error is assuming the speedup is always exactly 5x. In reality, the speedup is reduced by the time taken to fill the pipeline initially, the overhead of pipeline registers, and 'bubbles' caused by hazards like branches or data dependencies.

Why is it incorrect to say that pipelining makes individual instructions run faster?

Pipelining does not reduce the execution time of a single instruction; in fact, the overhead of moving data between stages can make a single instruction take slightly longer. Its benefit comes from overlapping multiple instructions so that the overall work finished per second is higher.

What happens to the pipeline if a branch prediction is incorrect?

If a prediction is wrong, the processor must perform a 'pipeline flush.' This involves discarding all instructions that were incorrectly fetched after the branch and restarting the fetch process from the correct target address, resulting in lost clock cycles.

Define a 'Pipeline Bubble'.

A pipeline bubble, or stall, is a delay inserted into the pipeline to resolve a hazard. During a bubble, no useful work is performed in the affected stages, which prevents subsequent instructions from advancing until the hazard is cleared.

What are Pipeline Registers (Latches)?

These are high-speed storage elements placed between each stage of the pipeline. They hold the intermediate results and control signals of an instruction so that the next stage can process them in the following clock cycle while the previous stage starts a new instruction.

What is the 'Fetch-Decode-Execute' cycle in a pipelined processor?

It is the standard sequence of steps a CPU takes to process an instruction, which in a pipelined architecture is split into independent stages so that while one instruction is being executed, the next is being decoded and the one after is being fetched.

Why does a branch instruction cause a 'Control Hazard'?

A control hazard occurs because the processor does not know the outcome of a conditional branch (whether it will jump or not) until the instruction reaches the execution stage. By that time, the next few instructions have already been fetched, and if the branch is taken, those instructions are invalid.

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1. The Characteristics of Contemporary Processors, Input, Output & Storage Devices

Pipelining

Summary

Pipelining is a fundamental processor architecture technique that increases instruction throughput by overlapping the execution of multiple instructions. By dividing the instruction cycle into discrete stages, the CPU can process different parts of several instructions simultaneously, significantly improving performance without necessarily reducing the time taken for a single instruction to complete.

1. Definition & Core Concepts

Pipelining is an implementation technique where multiple instructions are overlapped in execution, similar to an industrial assembly line.
The standard instruction cycle is divided into discrete stages, typically including Fetch (retrieving the instruction), Decode (interpreting the opcode), and Execute (performing the operation).
In a pipelined system, as soon as the first instruction moves from the Fetch stage to the Decode stage, the next instruction can enter the Fetch stage.
This concurrency ensures that different hardware resources within the CPU are utilized at every clock cycle, rather than sitting idle while a single instruction completes its entire cycle.

Diagram showing three instructions overlapping in a 3-stage pipeline across multiple clock cycles.

2. Underlying Principles

3. Pipeline Hazards

Structural Hazards: These occur when the hardware cannot support all possible combinations of instructions in the same clock cycle, such as two instructions needing to access memory simultaneously.
Data Hazards: These arise when an instruction depends on the result of a previous instruction that is still moving through the pipeline. A common type is Read After Write (RAW), where an instruction tries to read a register before a previous instruction has written to it.
Control Hazards: Also known as branch hazards, these occur when the pipeline makes the wrong decision on a conditional branch, fetching instructions that should not be executed.
Pipeline Flush: When a branch is taken, the instructions already in the pipeline (which were fetched sequentially) must be discarded, causing a performance penalty.

4. Methods & Techniques

5. Key Distinctions

6. Exam Strategy & Tips